1. Technical Field
The present invention relates generally to semiconductor manufacture, and more particularly, to the formation of a sublithographic trench in a semiconductor substrate.
2. Related Art
A number of processes have been proposed for patterning, featuring dimensions that are smaller than those obtainable by conventional photolithography. For example, sidewall image transfer is available for patterning layers by subtractive etching. However, this process is not suitable for producing sublithographic trenches. Because trench patterns are widely used in a number of applications, such as making damascene gates, damascene interconnects, isolation trenches, etc., it would be desirable to have a process that could be employed to achieve trenches with sublithographic dimensions.
Typically, when trenches having sublithographic dimensions have been formed, it has occurred as an undesirable artifact of an etching process. For example, during polysilicon gate etch with a high density plasma reactor, ions reflecting off sidewalls can cause increased etching at the periphery of the feature and possibly trenching into the underlying substrate. Such microtrenching into the substrate can adversely affect device performance and reliability. See, for example, U.S. Pat. No. 5,895,273, for a discussion of microtrenching problems. In this context, microtrenching has been studied, with the objective being to avoid or overcome it as undesirable. See also, J. -H. Lee, et al. Effects Of Buffer Layer Structure On Polysilicon Buffer LOCOS For The Isolation Of Submicron Silicon Devices, IEEE Transactions On Electron Devices, Vol. 45, No. 10, October 1998, pp. 2153-2160; I. J. Gupta, et al., A Comprehensive Assessment of Microtrenching During High Density Polysilicon Etch, 3rd International Symposium on Plasma Process-Induced Damage, June 1998, pp. 84-87, and Morioka, et al., Effect of Wafer Bias Frequency On Microtrenching During High Selective Gate Etching, 4th International Symposium On Plasma-Process Induced Damage, May 1999, pp. 159-162.
On the contrary, approaches attempting to use microtrenching, rather than avoiding it, are described in U.S. Pat. No. 5,736,418 and Eur. Pat. Appln., Pub. No. EP 0 632 495 A2. In the first reference, Microtrenches are formed in an effort to control hot electron effects and in the second, microtrenches are formed, then filled, to form isolation structures. Neither, however, uses the microtrenches for further etching definition and control.
Therefore, there exists a need in the industry for an improved method of making a sublithographic trench, without adding an unreasonable number of steps, while at the same time addressing other manufacturing problems such as microtrenching.
It is against this background that the present invention introduces a method of forming a sublithographic trench by first forming a microtrench, which is subsequently used as a mask. In particular, in accordance with the invention, there is provided a method of forming a sublithographic trench in a semiconductor substrate, comprising the steps of: forming a selectively etchable layer on the substrate; forming a masking layer on the selectively etchable layer; forming a pattern in the masking layer; using the pattern to partially etch the selectively etchable layer to form a microtrench therein; and using the microtrench as a mask to etch a sublithographic trench in the substrate.
Further, in accordance with the invention, there is provided a trench formed in a semiconductor substrate, the trench having a width which is sublithographic and corresponds to the width of a micotrench etched into a selectively etchable layer over the substrate.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of embodiments of the invention.